The present invention relates to a semiconductor memory, and more particularly, to a static memory provided with a bus line coupling noise canceller.
FIG. 1 is a block diagram of a known static RAM having a power-down mode. In FIG. 1, an external address input which is applied to a terminal 15 is provided to a row address buffer circuit 3 and its internal address output is supplied to a row decoder circuit 2, wherein it selects a row. In a similar manner, an external address input is applied to a terminal 16 and is then applied via a column address buffer circuit 4 to a column decoder circuit 5 for the selection of a column. External data input Din which is provided to a terminal 17, is applied to a data input circuit 7, by which valid data are written into selected cell. An external select input CS is provided to a terminal 18 and is then applied via a chip select circuit 8 to the row decoder circuit 2, the column address buffer circuit 4, the column decoder circuit 5 and a sense circuit 10 for controlling these circuits and to save power. An external write input is applied to a terminal 19 and is then provided via a write circuit 9 to the data input circuit 7 and an output circuit 11 to control those circuits. Further, the chip select circuit 8 controls the data input circuit 7 and the write circuit 9 at the same time.
A memory cell array comprises a static semiconductor having memory cells, each formed by a flip-flop, and respectively connected to intersections of pluralities of word lines and bit line pairs. FIG. 2 shows a part of the static semiconductor memory. In FIG. 2, reference characters W.sub.1, W.sub.2, . . . indicate word lines; B.sub.11 and B.sub.12 designate a pair of bit lines; and MC.sub.11, MC.sub.12, . . . identify memory cells respectively connected to the inter-sections of the word lines and the bit lines pairs. The pair of bit lines B.sub.11 and B.sub.12 is connected at one end to a power source Vcc respectively via transistors Q.sub.11 and Q.sub.12 serving as load transistors and at the other end to a sense amplifier SA respectively via transistors Q.sub.13 and Q.sub.14 forming transfer gates for column (bit line) selection use.
In a static memory having a power-down mode, a circuit for controlling the transfer gates Q.sub.13 and Q.sub.14 and the sense amplifier SA is arranged as shown in FIG. 3. In a column decoder, a NOR gate NG.sub.1 for column selection use, a transistor Q.sub.22 is turned ON and OFF by a signal CS.sub.2 derived from a chip select signal, and is connected between a gate for receiving a column address input CAI and a load transistor Q.sub.21. When a chip including the illustrated memory cell is not selected, the transistor Q.sub.22 is held in the OFF state, preventing power consumption by the NOR gate NG.sub.1. Also in the sense amplifier SA, a transistor Q.sub.23 turned ON and OFF by the signal CS.sub.2, is provided to prevent power consumption by the sense amplifier SA while the chip is not selected. Reference characters DB.sub.1 and DB.sub.2 indicate data buses, which are also connected to other bit line pairs via transfer gates similar to those Q.sub.13 and Q.sub.14 though not shown. Reference characters Q.sub.24 and Q.sub.25 designate transistors which are connected between the power source Vcc and the data buses to supply potentials to the data buses so that they do not become floating. Reference characters SD and SDB identify a pair of outputs or buses.
In this memory circuit, when the chip is being selected, the signal CS.sub.2 is high-level and the transistor Q.sub.22 is in the ON state. When the illustrated column of the memory is selected, the NOR gate NG.sub.1 is turned OFF and when the column is not selected, the NOR gate NG.sub.1 is in the ON state. When the NOR gate NG.sub.1 is in the OFF state, the transistors Q.sub.13 and Q.sub.14 are turned ON by a high-level voltage of the power source Vcc applied thereto via the load transistor Q.sub.21. As a consequence, the potentials of the bit lines B.sub.11 and B.sub.12 which become high- or low-level dependent on the stored content of a memory cell selected by the word line, are transmitted to the data buses DB.sub.1 and DB.sub.2, amplified by the sense amplifier SA and then outputted to the buses SD and SDB. If the illustrated column is not selected, then the NOR gate NG.sub.1 is held in the ON state, so that transistors Q.sub.13 and Q.sub.14 have their gates grounded, thus disconnecting the bit lines B.sub.11 and B.sub.12 from the data buses DB.sub.1 and DB.sub.2. Since the transistors Q.sub.13 and Q.sub.14 are of the enhancement type (depletion type transistors being marked with a dot .cndot.), when they are in the ON state (their gate potentials being equal to the power source) the potentials of the bit lines B.sub.11 and B.sub.12 are lowered by a threshold voltage Vth of each of the transistors Q.sub.11, Q.sub.12 and Q.sub.13, Q.sub.14 and Q.sub.24, Q.sub.25 and data is transferred from the bit lines B.sub.11 and B.sub.12 to the data buses DB.sub.1 and DB.sub.2 at that lowered potential.
Now, let it be assumed that the chip including the illustrated memory cell, is placed in its nonselected, standby, state from the selected state. Between the gate and the source-drain path of each of the transistors Q.sub.13 and Q.sub.14 exists an electrostatic capacitance C due to an overlap. When the gate potentials of the transistors Q.sub.13 and Q.sub.14 are low-level, that is, when the chip is selected but the column is not selected, the capacitances C are charged up to the potentials of the data buses DB.sub.1 and DB.sub.2. In this state, when the chip becomes nonselected, standby the signal CS.sub.2 becomes low-level and the transistor Q.sub.22 is turned OFF, so that the gate potentials of the transistors Q.sub.13 and Q.sub.14 rise up to the voltage level of the power source Vcc. This not only turns ON the transistors Q.sub.13 and Q.sub.14 but also causes a bootstrap operation, by which the data buses DB.sub.1 and DB.sub.2 are charged by way of the power source, the transistor Q.sub.21 and the charged capacitances C up to a level higher than the level (Vcc-Vth) which is lowered by the threshold voltage Vth of the transistors Q.sub.13 and Q.sub.14 from power source Vcc level. Since the prior art memory is not provided with a discharge circuit for this overcharging of the data buses, they remain in this ultra-high level state.
The overcharging of the data buses DB.sub.1 and DB.sub.2 also occurs in the sense amplifier SA, because there exist overlap capacitances C between the gates and the source-drain paths of transistors Q.sub.26 and Q.sub.27 of the sense amplifier SA. When the signal CS.sub.2 is high-level and the transistor Q.sub.23 is in the ON state, that is, when the sense amplifier SA is in operation, the capacitances C are charged by differences between the potentials of the data buses DB.sub.1 and DB.sub.2 and the potential at a node N.sub.2, i.e. the connection point of the source of the transistors Q.sub.26 and Q.sub.27. When the chip becomes nonselected, the transistor Q.sub.23 is turned OFF and the potential at the node N.sub.2 is raised by load transistors Q.sub.28 and Q.sub.29 and the driven transistors Q.sub.26 and Q.sub.27 towards the power source potential and, by the stored charges of the capacitances C, the data buses DB.sub.1 and DB.sub.2 are overcharged.
If the potentials of the data are raised too high, there is the possibility that when the chip selection and the column selection are made, the sense amplifier SA reads first a difference between previous data which was selected during the previous cycle, resulting in time for an access in the chip select access mode lagging the access time for the chip select access mode where the buses are not stored charge by the above described coupling.